1. Field of the Invention
The invention relates to the field of semiconductor memories as fabricated in integrated circuits and more particularly to a read-only memory and a method for fabricating the same at a high number of devices per unit area of semiconductor chip, i.e. high device density.
2. Description of the Prior Art
Ever since the invention of a first integrated circuit, the micro-miniaturization of semiconductor circuits, particularly digital memories, has progressed by decreasing the size of the semiconductor chip allocated to each memory cell and/or increasing the size of the chip.
The ability to increase the size of the chip is typically limited by substantial loss in yield as the chip area increases. Attempts to decrease the sources of defects in the chips, which cause yields to suffer, have been very complex and uneconomically expensive.
Similarly, substantial efforts in the integrated circuit industry in reducing the size of individual circuit components within a given area have reached and pushed the inherent limitations of electron beam lithography or X-ray lithography in the attempt to reliably fabricate components with geometries of less than two microns in any one dimension. Further micro-miniaturization beyond a two-micron rule or step has thus far been exceedingly expensive and generally limited by the inherent effects of electron scattering and proximity effects within the semiconductor devices thus fabricated.
As a result, substantial efforts have been undertaken to derive suitable designs for a memory cell within a read- only memory which can be reliably fabricated in high densities within the inherent limitations of current manufacturing techniques. Examples of such designs are shown in Roesner, "Method of Forming a Metal Semiconductor Field Effect Transistor", U.S. Pat. No. 4,358,891 (1982); Roesner, "Mask Programmable Read-Only Memory Stacked above a Semiconductor Substrate", U.S. Pat. No. 4,424,579 (1984); Roesner et al., "Reduced-Area, Read-Only Memory", U.S. Pat. No. 4,598,386 (1986); and Roesner, "Electrically Programmable Read-Only Memory Stacked above a Semiconductor Substrate", U.S. Pat. No. 4,442,507 (1984), each of which references are herein expressly incorporated by reference for the enablement purpose of the present disclosure.
The relevance of the prior art is best understood in the context of the art as shown by Roesner '507. Refer particularly to FIG. 11 of that patent, a version of which is recreated here as FIG. 1, and which shows two adjacent cells. The cells are disposed in an insulating substrate 10 on which a heavily N doped word line 12 has been disposed within an etched cavity in an overlying insulating layer 14. A lightly N doped diode layer 16 is disposed on and in contact with word line 12. The width, as seen through the cross-sectional view of FIG. 1, of each cell, as defined by its word line width, is approximately 4 microns. A space of 2 microns separates the two adjacent cells, since the 2-micron rule dictates that the minimum spacing which can be reliably defined by present commercial production techniques is 2 microns.
A silicide of a noble metal is disposed within the aperture 18 of each cell in contact with diode layer 16. A Schottky diode is thus formed within the boundaries defined by layers 12 and 16.
Therefore, the total distance which is required between Schottky diodes is the amount of space determined by the misalignment of metallic layer 20 with respect to layers 12 and 16, which for a 2-micron process must never be less than at least 1 micron.
Lightly N-doped programmable material 22 selected from the group of silicon, germanium, carbon and alpha-tin is then disposed over metallic layer 20. Material 22 exhibits a relatively high resistance so long as the voltage across it does not exceed the threshold level. However, once the threshold voltage is exceeded, the resistance of material 22 irreversibly switches from a high resistance state to a relatively low resistance state.
A metallic address line 24 is then disposed upon and connects with programmable material 22 to complete the memory structure as more completely described in Roesner '507.
Very clearly, based upon fabrication methodologies and circuit structures which have heretofore existed, a memory comprised of devices such as shown in FIG. 1 cannot be fabricated with a greater density than that which allowed approximately 6 microns between the center of one cell and the next adjacent cell.
Therefore, what is needed is a design for a semiconductor memory and a structure for a memory cell whereby the defects of the prior art are overcome and wherein more particularly a higher density read-only memory can be fabricated using a conventional 2-micron process.